EEVblog #1247 - DDR Memory PCB Propagation Delay & Layout

When does PCB propagation delay matter in PCB layout?
Dave goes down the rabbit hole from DIY TTL processor design to DDR memory design and layout.
DDR memory termination.
What is a timing budget? When is it important?
How does signal integrity matter?
When do you have to do serpentine PCB traces to match trace and differential pair lengths?

Micron DDR memory timing budget design:
https://www.micron.com/-/media/client/global/documents/products/technical-note/dram/tn4611.pdf
The CIAA Project https://github.com/ciaa/Hardware/tree/master/PCB/ACC/CIAA_ACC
How to lay out a PCB: https://www.youtube.com/watch?v=JrH_itjMDjo

Forum: https://www.eevblog.com/forum/blog/eevblog-1247-ddr-memory-pcb-propagation-delay-layout/

#PCB #Layout #DDRmemory

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