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CEVA Video Dynamic range compression demo

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CEVA Video Dynamic range compression demo

C
CEVA, Inc.

6 Views • Jul 16, 2014

Description

The demonstration shown here shows DRC being performed entirely in software, written in C, and no hardware acceleration is required. The demonstration uses a single vector processor core that performs filtering and the vector-type operations required for pixel processing. It is shown implemented on an FPGA and operating at 80MHz.

https://www.youtube.com/watch?v=NtRT8W5AIRY&list=UUYxDQ8HHEB6KvQzxylJnpGg