CEVA Video Dynamic range compression demo

The demonstration shown here shows DRC being performed entirely in software, written in C, and no hardware acceleration is required. The demonstration uses a single vector processor core that performs filtering and the vector-type operations required for pixel processing. It is shown implemented on an FPGA and operating at 80MHz.

https://www.youtube.com/watch?v=NtRT8W5AIRY&list=UUYxDQ8HHEB6KvQzxylJnpGg